upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 62

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

3.2.2 System register set
load/store instruction (LDSR or STSR instruction).
(1) Interrupt source register (ECR)
After reset: 00000000H
62
Symbol
ECR
6 to 31
System registers control the status of the CPU and hold interrupt information.
To read/write these system registers, specify the system register number indicated by the system register
No.
0
1
2
3
4
5
31
EIPC
EIPSW
FEPC
FEPSW
ECR
PSW
Reserved
System Register Name
FECC
EICC
Exception code of NMI (For the exception code, refer to Table 5-1.)
Exception code of exception/interrupt
FECC
Interrupt source register
Program status word
Interrupt status saving registers
NMI status saving registers
Table 3-2. System Register Numbers
CHAPTER 3 CPU FUNCTIONS
User’s Manual U12768EJ4V1UD
Usage
16
15
These registers save the PC and PSW when an
exception or interrupt occurs. Because only one set of
these registers is available, their contents must be
saved when multiple interrupts are enabled.
These registers save the PC and PSW when an NMI
occurs.
If an exception, maskable interrupt, or NMI occurs, this
register
interrupt source. The higher 16 bits of this register are
called FECC, to which the exception code of the NMI is
set. The lower 16 bits are called EICC, to which the
exception code of the exception/interrupt is set.
The program status word is a collection of flags that
indicate the program status (instruction execution
result) and CPU status.
EICC
will
contain
Operation
information
0
referencing
the