upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 136

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

5.8.1 Interrupt request valid timing after EI instruction
(interrupts disabled) and interrupts are not masked (MK flag = 0), seven system clocks are required from the execution
of the EI instruction (interrupts enabled) to the interrupt request acknowledgement by the CPU. The CPU does not
acknowledge interrupt requests if the DI instruction (interrupts disabled) is executed during the seven system clocks.
(interrupts enabled). However, under the following conditions, interrupt requests cannot be acknowledged even if the
seven system clocks are secured, so securing under the following conditions is prohibited.
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When an interrupt request signal is generated (IF flag = 1) in the status in which the DI instruction is executed
Therefore, seven system clocks worth of instruction execution clocks must be inserted after the EI instruction
• In IDLE/software STOP mode
• An interrupt request non-sampling instruction (instruction to manipulate the PSW.ID bit) is executed
• An interrupt request control register (xxICn) is accessed
The following shows an example of program processing.
[Program processing example]
Note Do not execute the DI instruction (PSW.ID = 1) during this period.
Remarks 1. In this example, the DI instruction is executed at the eighth clock after execution of the EI instruction,
LP1 :
DI
:
:
EI
NOP
NOP
NOP
NOP
JR
:
DI
2. The interrupt servicing routine instructions are not executed at the eighth clock after the EI
3. This example shows the case in which an interrupt request signal is generated (IF flag = 1) before
so the CPU acknowledges an interrupt request signal and performs interrupt servicing.
instruction execution. The interrupt servicing routine instructions are executed the four system
clocks after the CPU acknowledges the interrupt request signal.
the EI instruction is executed. If an interrupt request signal is generated after the EI instruction is
executed, the CPU does not acknowledge the interrupt request signal if interrupts are disabled
(PSW.ID = 1) for seven clocks after the IF flag is set (1).
LP1
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
; (MK flag = 0)
; ← Interrupt request occurs (IF flag = 1)
; EI instruction executed
; 1 system clock
; 1 system clock
; 1 system clock
; 1 system clock
; 3 system clocks (branch to LP1 routine)
; LPI routine
; After EI instruction execution, NOP instruction is
executed four times, and DI
instruction is executed at the eighth clock by JR instruction
User’s Manual U12768EJ4V1UD
Note