upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 97

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

4.7.2 Bus hold procedure
4.7.3 Operation in power save mode
even if the HLDRQ pin becomes active.
hold status is set. When the HLDRQ pin becomes inactive, the HLDAK pin becomes inactive. As a result, the bus
hold status is cleared, and the HALT mode is set again.
The procedure of the bus hold function is illustrated below.
In the IDLE or software STOP mode, the system clock is stopped. Consequently, the bus hold status is not set
In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the bus
HLDRQ
<1>HLDRQ = 0 acknowledged
<2>All bus cycle start requests held pending
<3>End of current bus cycle
<4>Bus idle status
<5>HLDAK = 0
<6>HLDRQ = 1 accepted
<7>HLDAK = 1
<8>Clears pending bus cycle start requests
<9>Start of bus cycle
HLDAK
CHAPTER 4 BUS CONTROL FUNCTION
Figure 4-7. Bus Hold Procedure
User’s Manual U12768EJ4V1UD
<1> <2> <3><4><5>
<6>
<7><8><9>
Normal status
Bus hold status
Normal status
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