uja1061 NXP Semiconductors, uja1061 Datasheet - Page 14

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1061_5
Product data sheet
6.4.3 Watchdog time-out behavior
6.4.4 Watchdog OFF behavior
The watchdog window is defined to be between 50 % and 100 % of the nominal
programmed watchdog period. Any too early or too late watchdog access or wrong Mode
register code access will result in an immediate system reset, entering Start-up mode.
Whenever the SBC operates in Standby mode, in Sleep mode or in Flash mode, the active
watchdog operates in Time-out mode. The watchdog has to be triggered within the actual
programmed period time; see
wake-up events to the host microcontroller from Standby and Sleep mode.
In Standby and in Flash mode the nominal periods can be changed with any SPI access
to the Mode register.
Any illegal watchdog trigger code results in an immediate system reset, entering Start-up
mode.
In Standby and Sleep mode it is possible to switch off the watchdog entirely. For fail-safe
reasons this is only possible if the microcontroller has stopped program execution. To
ensure that there is no program execution, the V1 supply current is monitored by the SBC
while the watchdog is switched off.
When selecting the watchdog OFF code, the watchdog remains active until the
microcontroller supply current has dropped below the current monitoring threshold I
After the supply current has dropped below the threshold, the watchdog stops at the end
of the watchdog period. In case the supply current does not drop below the monitoring
threshold, the watchdog stays active.
If the microcontroller supply current increases above I
the watchdog is restarted with the last used watchdog period time and a watchdog restart
interrupt is forced, if enabled.
Fig 5. Watchdog triggering using Time-out mode
(with different duration if
trigger
via SPI
trigger restarts period
possible
earliest
trigger
point
desired)
Rev. 05 — 22 November 2007
trigger range
Figure
period
Fault-tolerant CAN/LIN fail-safe system basis chip
5. The Time-out mode can be used to provide cyclic
trigger range
new period
possible
trigger
latest
point
time-out
thH(V1)
while the Watchdog is OFF,
© NXP B.V. 2007 Nov 23. All rights reserved.
UJA1061
time-out
mce627
thL(V1)
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