uja1061 NXP Semiconductors, uja1061 Datasheet - Page 26

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1061_5
Product data sheet
Fig 13. Pin WAKE, cyclic sampling via V3
sample
V
flip flop
V
active
WAKE
INTN
6.11 Interrupt output
6.12 Temperature protection
V
3
If V3 is continuously ON, the WAKE input will be sampled continuously, regardless of the
level of bit WSC.
The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the
System Status register reflect the actual status of pin WAKE. The WAKE port can be
disabled by clearing the WEN bit in the System Configuration register.
Pin INTN is an open-drain interrupt output. It is forced LOW whenever at least one bit in
the Interrupt register is set. By reading the Interrupt register all bits are cleared. The
Interrupt register will also be cleared during a system reset (RSTN LOW).
As the microcontroller operates typically with an edge-sensitive interrupt port, pin INTN
will be HIGH for at least t
interrupts within t
To prevent the microcontroller from being slowed down by repetitive interrupts, in Normal
mode some interrupts are only allowed to occur once per watchdog period; see
Section
If an interrupt is not read out within t
The temperature of the SBC chip is monitored as long as the microcontroller voltage
regulator V1 is active. To avoid an unexpected shutdown of the application by the SBC,
the temperature protection will not switch-off any part of the SBC or activate a defined
system stop of its own accord. If the temperature is too high it generates an interrupt to
the microcontroller ( C), if enabled, and the corresponding status bit will be set. The
microcontroller can then decide whether to switch-off parts of the SBC to decrease the
chip temperature.
signal already HIGH
due to biasing (history)
t
su(CS)
t
on(CS)
6.13.7.
approximately 70 %
t
w(CS)
INTNH
Rev. 05 — 22 November 2007
pin INTN stays HIGH, otherwise it will revert to LOW again.
INTN
button pushed
after each read-out of the Interrupt register. Without further
Fault-tolerant CAN/LIN fail-safe system basis chip
RSTN(INT)
button released
signal remains LOW
due to biasing (history)
a system reset is performed.
© NXP B.V. 2007 Nov 23. All rights reserved.
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