uja1061 NXP Semiconductors, uja1061 Datasheet - Page 25

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1061_5
Product data sheet
Fig 12. States of the INH/LIMP pin
6.8.6.3 LIN recessive clamping
6.10 Wake-up input
6.9 Inhibit and limp home output
INH/LIMP:
ILEN = 1
ILC = 1
HIGH
If the LIN bus pin is clamped recessive while TXDL is driven dominant the LIN transmitter
is disabled. The transmitter is reactivated automatically when the LIN bus becomes
dominant or manually by setting and clearing the LTC bit.
The INH/LIMP output pin is a 3-state output pin which can be used either as an inhibit for
an extra (external) voltage regulator, or as a ‘limp home’ output. The pin is controlled via
the ILEN bit and ILC bit in the System Configuration register; see
When pin INH/LIMP is used as inhibit output, a pull down resistor to GND ensures a
default LOW level. The pin can be set to HIGH according to the state diagram.
When pin INH/LIMP is used as limp home output, a pull up resistor to V
default HIGH level. The pin is automatically set to LOW when the SBC enters Fail-safe
mode.
The WAKE input comparator is triggered by negative edges on pin WAKE. Pin WAKE has
an internal pull-up resistor to BAT42. It can be operated in two sampling modes which are
selected via the WAKE Sample Control bit (WSC):
•
•
state change via SPI
Continuous sampling (with an internal clock) if the bit is set
Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see
This is to save bias current within the external switches in low-power operation. Two
repetition times are possible, 16 ms and 32 ms.
power-on
OR (enter Start-up mode after
wake-up reset, external reset
OR enter Restart mode
OR enter Sleep mode
state change via SPI
or V1 undervoltage)
Rev. 05 — 22 November 2007
OR enter Fail-safe mode
state change via SPI
state change via SPI
INH/LIMP:
floating
ILC = 1/0
ILEN = 0
Fault-tolerant CAN/LIN fail-safe system basis chip
OR enter Fail-safe mode
state change via SPI
state change via SPI
001aad178
INH/LIMP:
ILEN = 1
ILC = 0
LOW
Figure
© NXP B.V. 2007 Nov 23. All rights reserved.
UJA1061
BAT42
12.
ensures a
Figure
25 of 74
13.