uja1061 NXP Semiconductors, uja1061 Datasheet - Page 29

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 5.
[1]
[2]
Table 6.
UJA1061_5
Product data sheet
Bit
15 and 14
13
12
11 to 6
5 to 3
2
1
0
Bit
11 to 6
Flash mode can be entered only with the watchdog service sequence ‘Normal mode to Flash mode to Normal mode to Flash mode’,
while observing the watchdog trigger rules. With the last command of this sequence the SBC forces a system reset, and enters Start-up
mode to prepare the microcontroller for flash memory download. The four RSS bits in the System Status register reflect the reset source
information, confirming the Flash entry sequence. By using the Initializing Flash mode (within t
now successfully enter Flash mode.
See
Section
Mode register bit description (bits 15 to 12 and 5 to 0)
Mode register bit description (bits 11 to 6)
Symbol
A1, A0
RRS
RO
NWP[5:0]
OM[2:0]
SDM
EN
-
Symbol
NWP[5:0]
6.14.1.
Description
register address
Read Register
Select
Read Only
see
Operating Mode
Software
Development
Mode
Enable
reserved
Description
Nominal
Watchdog Period
WDPRE = 00 (as
set in the Special
Mode register)
Table 6
Value
00
1
0
1
0
001
010
011
100
101
110
111
1
0
1
0
0
Value
00 1001
00 1100
01 0010
01 0100
01 1011
10 0100
10 1101
11 0011
11 0101
11 0110
Rev. 05 — 22 November 2007
[1]
Function
select Mode register
read System Diagnosis register
read System Status register
read selected register without writing to Mode register
read selected register and write to Mode register
Normal mode
Standby mode
initialize Flash mode
Sleep mode
initialize Normal mode
leave Flash mode
Flash mode
Software Development mode enabled
normal watchdog, interrupt, reset monitoring and fail-safe
behavior
EN output pin HIGH
EN output pin LOW
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
Time
Normal
mode (ms)
4
8
16
32
40
48
56
64
72
80
Fault-tolerant CAN/LIN fail-safe system basis chip
[1]
Standby
mode (ms)
20
40
80
160
320
640
1024
2048
4096
OFF
[2]
[1]
WD(init)
Flash mode
(ms)
20
40
80
160
320
640
1024
2048
4096
8192
after system reset) the SBC will
[2]
© NXP B.V. 2007 Nov 23. All rights reserved.
UJA1061
Sleep mode
(ms)
160
320
640
1024
2048
3072
4096
6144
8192
OFF
[3]
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