uja1061 NXP Semiconductors, uja1061 Datasheet - Page 30

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 6.
[1]
[2]
[3]
UJA1061_5
Product data sheet
Bit
11 to 6
The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for f
See
The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is
immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry
without dips on V1; see
Section
Mode register bit description (bits 11 to 6)
Symbol
NWP[5:0]
6.4.4.
Section
Description
Nominal
Watchdog Period
WDPRE = 01 (as
set in the Special
Mode register)
Nominal
Watchdog Period
WDPRE = 10 (as
set in the Special
Mode register)
Nominal
Watchdog Period
WDPRE = 11 (as
set in the Special
Mode register)
6.4.4.
Value
00 1001
00 1100
01 0010
01 0100
01 1011
10 0100
10 1101
11 0011
11 0101
11 0110
00 1001
00 1100
01 0010
01 0100
01 1011
10 0100
10 1101
11 0011
11 0101
11 0110
001001
001100
010010
010100
011011
100100
101101
110011
110101
110110
Rev. 05 — 22 November 2007
[1]
(Continued)
Time
Normal
mode (ms)
6
12
24
48
60
72
84
96
108
120
10
20
40
80
100
120
140
160
180
200
14
28
56
112
140
168
196
224
252
280
Fault-tolerant CAN/LIN fail-safe system basis chip
Standby
mode (ms)
30
60
120
240
480
960
1536
3072
6144
OFF
50
100
200
400
800
1600
1560
5120
10240
OFF
70
140
280
560
1120
2240
3584
7168
14336
OFF
[2]
[2]
[2]
Flash mode
(ms)
30
60
120
240
480
960
1536
3072
6144
12288
50
100
200
400
800
1600
1560
5120
10240
20480
70
140
280
560
1120
2240
3584
7168
14336
28672
© NXP B.V. 2007 Nov 23. All rights reserved.
osc
UJA1061
= 512 kHz.
Sleep mode
(ms)
240
480
960
1536
3072
4608
6144
9216
12288
OFF
400
800
1600
2560
5120
7680
10240
15360
20480
OFF
560
1120
2240
3584
7168
10752
14336
21504
28672
OFF
[3]
[3]
[3]
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