uja1061 NXP Semiconductors, uja1061 Datasheet - Page 15

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1061_5
Product data sheet
6.5.1 RSTN pin
6.5 System reset
In case of a direct mode change towards Standby mode with watchdog OFF selected, the
longest possible watchdog period is used. It should be noted that in Sleep mode V1
current monitoring is not active.
The reset function of the UJA1061 offers two signals to deal with reset events:
The system reset pin (RSTN) is a bidirectional input / output. Pin RSTN is active LOW
with selectable pulse length upon the following events; see
All of these reset events have a dedicated reset source in the System Status register to
allow distinction between the different events.
The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware
is properly reset. After the first battery connection, a short power-on reset of 1 ms is
provided after voltage V1 is present. Once started, the microcontroller can set the Reset
Length Control (RLC) bit within the System Configuration register; this allows the reset
pulse to be adjusted for future reset events. With this bit set, all reset events are
lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatically to 20 ms in
Restart or Fail-Safe mode. With this mechanism it is guaranteed that an erroneously
shortened reset pulse will restart any microcontroller, at least within the second trial by
using the long reset pulse.
The behavior of pin RSTN is illustrated in
setting of the RLC bit (defines the reset length). Once an external reset event is detected
the system controller enters the Start-up mode. The watchdog now starts to monitor pin
RSTN as illustrated in
mode is entered as shown in
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RSTN; the global ECU system reset
EN; a fail-safe global enable signal
Power-on (first battery connection) or BAT42 below power-on reset threshold voltage
Low V1 supply
V1 current above threshold during Standby mode while watchdog OFF behavior is
selected
V3 is down due to short-circuit condition during Sleep mode
RSTN externally forced LOW, falling edge event
Successful preparation for Flash mode completed
Successful exit from Flash mode
Wake-up from Standby mode via pins CAN, LIN or WAKE if programmed accordingly,
or any wake-up event from Sleep mode
Wake-up event from Fail-safe mode
Watchdog trigger failures (too early, overflow, wrong code)
Illegal mode code via SPI applied
Interrupt not served within t
Rev. 05 — 22 November 2007
Figure
Figure
7. If the RSTN pin is not released in time then Fail-safe
RSTN(INT)
Fault-tolerant CAN/LIN fail-safe system basis chip
3.
Figure
6. The duration of t
Figure
3:
© NXP B.V. 2007 Nov 23. All rights reserved.
RSTNL
UJA1061
depends on the
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