uja1061 NXP Semiconductors, uja1061 Datasheet - Page 5

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
5. Pinning information
UJA1061_5
Product data sheet
5.1 Pinning
5.2 Pin description
Table 2.
Symbol
n.c.
n.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
SDO
SCK
SCS
TXDC
RXDC
n.c.
TEST
Fig 2. Pin configuration
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
not connected
not connected
LIN transmit data input (LOW for dominant, HIGH for recessive)
voltage regulator output for the microcontroller (3 V, 3.3 V or 5 V depending
on the SBC version)
LIN receive data output (LOW when dominant, HIGH when recessive)
reset output to microcontroller (active LOW; will detect clamping situations)
interrupt output to microcontroller (active LOW; open-drain, wire-AND this pin
to other ECU interrupt outputs)
enable output (active HIGH; push-pull, LOW with every reset / watchdog
overflow)
SPI data input
SPI data output (floating when pin SCS is HIGH)
SPI clock input
SPI chip select input (active LOW)
CAN transmit data input (LOW for dominant; HIGH for recessive)
CAN receive data output (LOW when dominant; HIGH when recessive)
not connected
test pin (should be connected to ground in application)
Rev. 05 — 22 November 2007
RXDC
RSTN
TXDC
RXDL
TXDL
TEST
INTN
SDO
SCK
SCS
SDI
n.c.
n.c.
n.c.
EN
V1
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061
001aad604
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BAT42
RESERVED
V3
SYSINH
n.c.
BAT14
RTLIN
LIN
RTH
GND
CANL
CANH
V2
RTL
WAKE
INH/LIMP
© NXP B.V. 2007 Nov 23. All rights reserved.
UJA1061
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