uja1061 NXP Semiconductors, uja1061 Datasheet - Page 21

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1061_5
Product data sheet
6.7.3 Termination control
6.7.4 Bus, RXD and TXD failure detection
The second pattern must be received within t
CAN-ID can be used with these data patterns.
If the CAN transceiver enters On-line Listen mode directly from Off-line mode the global
wake-up message is sufficient to wake-up the SBC. This pattern must be received within
t
global wake-up message, then both messages are required for a CAN wake-up.
In Active mode, On-line mode and On-line Listen mode, CANH is terminated to GND and
CANL is terminated to pin V2 via the external termination resistors applied to RTH and
RTL. In case of detected bus failures, the termination changes according to the ISO
11898-3 standard. In Off-line mode pin CANH stays terminated to GND but with a diode in
between (reverse supply protection) while pin CANL becomes terminated to pin BAT42
(via pin RTH and pin RTL). If pin V2 is disabled due to an overload condition RTH and RTL
become floating.
The UJA1061 can distinguish between bus, RXD and TXD failures as indicated in
All failures are signalled separately in the CANFD bits in the System Diagnosis register.
Any change (detection and recovery) forces an interrupt to the microcontroller, if this
interrupt is enabled.
Table 3.
[1]
Failure
HxVCC
HxBAT
HxGND
LxBAT
LxGND
LxVCC
HxL
H//
L//
Bus Dom
Bus Rec
TxDC Dom
RxDC Rec
RxDC Dom
timeout
CANL stays active with weak short-circuits to BAT due to wake-up requirements within large networks.
after entering On-line Listen mode. Should t
CAN-bus, RXD and TXD failure detection
Description
CANH to V
CANH to BAT (14 V and 42 V) short-circuit
CANH to GND short-circuit
CANL to BAT (14 V and 42 V) short-circuit
CANL to GND short-circuit
CANL to V
CANH to CANL short-circuit
CANH interrupted
CANL interrupted
bus is continuously clamped dominant
(double failure); even within Single-wire
mode the receiver remains dominant
bus is continuously clamped recessive
(double failure); driving messages to the bus
is not possible even while the driver is active
pin TXDC is continuously clamped dominant
(handles also RXDC to TXDC short-circuits)
pin RXDC is continuously clamped recessive transmitter disabled but no change in
pin RXDC is continuously clamped dominant none
Rev. 05 — 22 November 2007
CC
CC
(5 V) short-circuit
(5 V) short-circuit
Fault-tolerant CAN/LIN fail-safe system basis chip
timeout
timeout
after receiving the first pattern. Any
Driver and biasing circuit
disabling
CANH off, weak RTH
CANH off, weak RTH
none
CANL off, weak RTL
CANL off, weak RTL
none
CANL off, weak RTL
none
none
CANL off, weak RTL
none
transmitter disabled but no change in
biasing
biasing
elapse before receiving the
© NXP B.V. 2007 Nov 23. All rights reserved.
UJA1061
[1]
Table
21 of 74
3.