uja1061 NXP Semiconductors, uja1061 Datasheet - Page 36

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 11.
[1]
[2]
UJA1061_5
Product data sheet
Bit
15 and 14
13
12
11 and 10
9
8
7 and 6
5
4
3
2
1
0
RLC is set automatically with entering Restart mode or Fail-safe mode. This guarantees a safe reset period in case of serious failure
situations. External reset spikes are lengthened by the SBC until the programmed reset length is reached.
If WEN is not set, the WAKE port is completely disabled. There is no change of the bits EWS and WLS within the System Status
register.
System Configuration register and System Configuration Feedback register bit description
Symbol
A1, A0
RRS
RO
-
GSTHC
RLC
V3C[1:0]
-
V1CMC
WEN
WSC
ILEN
ILC
6.13.8 System Configuration register and System Configuration Feedback register
These registers allow configuration of the behavior of the SBC, and allow the settings to
be read back.
Description
register address
Read Register Select
Read Only
reserved
GND Shift Threshold
Control
Reset Length Control
V3 Control
reserved
V1 Current Monitor
Control
WAKE Enable
WAKE Sample Control
INH/LIMP Enable
INH/LIMP Control
[2]
Rev. 05 — 22 November 2007
Value
10
1
0
1
0
0
1
0
1
0
11
10
01
00
0
1
0
1
0
1
0
1
0
1
0
[1]
Function
select System Configuration register
read the General Purpose Feedback register 0
read the System Configuration Feedback register
read register selected by RRS without writing to System
Configuration register
read register selected by RRS and write to System
Configuration register
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
V
V
t
t
Cyclic mode 2; t
Cyclic mode 1; t
continuously ON
OFF
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
an increasing V1 current causes a reset if the watchdog
was disabled during Standby mode
an increasing V1 current just reactivates the watchdog
during Standby mode, and an interrupt is forced (if enabled)
WAKE pin enabled
WAKE pin disabled
WAKE mode cyclic sample
WAKE mode continuous sample
INH/LIMP pin active (see ILC bit)
INH/LIMP pin floating
INH/LIMP pin HIGH if ILEN bit is set
INH/LIMP pin LOW if ILEN bit is set
Fault-tolerant CAN/LIN fail-safe system basis chip
RSTNL
RSTNL
det(GSD)(CANH)
det(GSD)(CANH)
long reset lengthening time selected
short reset lengthening time selected
widened threshold
normal threshold
w(CS)
w(CS)
long period; see
short period; see
© NXP B.V. 2007 Nov 23. All rights reserved.
Figure 13
UJA1061
Figure 13
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