uja1061 NXP Semiconductors, uja1061 Datasheet - Page 6

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1061_5
Product data sheet
Table 2.
The exposed die pad at the bottom of the package allows better dissipation of heat from
the SBC via the printed-circuit board. The exposed die pad is not connected to any active
part of the IC and can be left floating, or can be connected to GND for the best EMC
performance.
Symbol
INH/LIMP
WAKE
RTL
V2
CANH
CANL
GND
RTH
LIN
RTLIN
BAT14
n.c.
SYSINH
V3
RESERVED
BAT42
Pin description (Continued)
Pin
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Description
inhibit / limp home output (BAT14 related, push-pull, default floating)
local wake-up input (BAT42 related, continuous or cyclic sampling)
CAN termination resistor connection; in case of a CANL bus wire error this
line is terminated with a selectable impedance
5 V voltage regulator output for CAN; connect a buffer capacitor to this pin
CANH bus line (HIGH in dominant state)
CANL bus line (LOW in dominant state)
ground
CAN termination resistor connection; in case of a CANH bus wire error this
line is terminated with a selectable impedance
LIN bus line (LOW in dominant state)
LIN-bus termination resistor connection
14 V battery supply input
not connected
system inhibit output (BAT42 related; e.g. for controlling external DC-to-DC
converter)
unregulated 42 V output (BAT42 related; continuous output, or cyclic mode
synchronized with local wake-up input)
must be connected to ground (GND)
42 V battery supply input (connect this pin to BAT14 in 14 V applications)
Rev. 05 — 22 November 2007
Fault-tolerant CAN/LIN fail-safe system basis chip
© NXP B.V. 2007 Nov 23. All rights reserved.
UJA1061
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