uja1061 NXP Semiconductors, uja1061 Datasheet - Page 3

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uja1061

Manufacturer Part Number
uja1061
Description
Low Speed Can/lin System Basis Chip
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
UJA1061_5
Product data sheet
2.4 Power management
2.5 Fail-safe features
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Smart operating modes and power management modes
Cyclic wake-up capability in Standby and Sleep mode
Local wake-up input with cyclic supply feature
Remote wake-up capability via the CAN-bus and LIN-bus
External voltage regulators can easily be incorporated in the power supply system
(flexible and fail-safe)
42 V battery related high-side switch for driving external loads such as relays and
wake-up switches
Intelligent maskable interrupt output
Safe and predictable behavior under all conditions
Programmable fail-safe coded window and time-out watchdog with on-chip oscillator,
guaranteeing autonomous fail-safe system supervision
Fail-safe coded 16-bit SPI interface for the microcontroller
Global enable pin for the control of safety critical hardware
Detection and detailed reporting of failures:
Rigorous error handling based on diagnostics
23 bits of access-protected RAM is available e.g. for logging of cyclic problems
Reporting in a single SPI message; no assembly of multiple SPI frames needed
Limp home output signal for activating application hardware in case system enters
Fail-safe mode (e.g. for switching on warning lights)
Fail-safe coded activation of Software development mode and Flash mode
Unique SPI readable device type identification
Software initiated system reset
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On-chip oscillator failure and watchdog alerts
Voltage regulator undervoltages
CAN and LIN-bus failures (short-circuits and open-circuit bus wires)
TXD and RXD clamping situations and short-circuits
Clamped or open reset line
SPI message errors
Overtemperature warning
ECU ground shift (two selectable thresholds)
Rev. 05 — 22 November 2007
Fault-tolerant CAN/LIN fail-safe system basis chip
© NXP B.V. 2007 Nov 23. All rights reserved.
UJA1061
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