uja1061 NXP Semiconductors, uja1061 Datasheet - Page 31

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 7.
UJA1061_5
Product data sheet
Bit
15 and 14
13
12
11 to 8
7
6
5
4
3
2
System Status register bit description
Symbol
A1, A0
RRS
RO
RSS[3:0]
CWS
LWS
EWS
WLS
TWS
SDMS
6.13.4 System Status register
This register allows status information to be read back from the SBC. This register can be
read in all modes.
Description
register address
Read Register Select
Read Only
Reset Source
CAN Wake-up Status
LIN Wake-up Status
Edge Wake-up Status
WAKE Level Status
Temperature Warning
Status
Software Development
Mode Status
[1]
Rev. 05 — 22 November 2007
Value
00
0
1
0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
0
1
0
1
0
1
0
1
0
1
0
Function
read System Status register
read System Status register without writing to Mode
register
read System Status register and write to Mode register
power-on reset; first connection of BAT42 or BAT42 below
power-on voltage threshold or RSTN was forced LOW
externally
cyclic wake-up out of Sleep mode
low V1 supply; V1 has dropped below the selected reset
threshold
V1 current above threshold within Standby mode while
watchdog OFF behavior and reset option (V1CMC bit) are
selected
V3 voltage is down due to overload occurring during Sleep
mode
SBC successfully left Flash mode
SBC ready to enter Flash mode
CAN wake-up event
LIN wake-up event
local wake-up event (via pin WAKE)
wake-up out of Fail-safe mode
watchdog overflow
watchdog not initialized in time; t
watchdog triggered too early; window missed
illegal SPI access
interrupt not served within t
CAN wake-up detected; cleared upon read
no CAN wake-up
LIN wake-up detected; cleared upon read
no LIN wake-up
pin WAKE negative edge detected; cleared upon read
pin WAKE no edge detected
pin WAKE above threshold
pin WAKE below threshold
chip temperature exceeds the warning limit
chip temperature is below the warning limit
Software Development mode on
Software Development mode off
Fault-tolerant CAN/LIN fail-safe system basis chip
RSTN(INT)
WD(init)
© NXP B.V. 2007 Nov 23. All rights reserved.
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