uja1061 NXP Semiconductors, uja1061 Datasheet - Page 22

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1061_5
Product data sheet
6.7.4.1 TXDC dominant clamping
6.7.4.2 RXDC recessive clamping
6.7.4.3 GND shift detection
6.8.1 Mode control
6.8 LIN transceiver
If the TXDC pin is clamped dominant for longer than t
disabled. After the TXDC pin becomes recessive the transmitter is reactivated
automatically when detecting bus activity or manually by setting and clearing the CTC bit.
If the RXDC pin is clamped recessive while the CAN bus is dominant the CAN transmitter
is disabled. The transmitter is reactivated automatically when RXDC becomes dominant
or manually by setting and clearing the CTC bit.
The SBC can detect ground shifts in reference to the CAN bus. Two different ground shift
detection levels can be selected with the GSTHC bit in the System Configuration register.
The failure can be read out in the System Diagnosis register. Any detected or recovered
GND shift event is signalled with an interrupt, if enabled.
The integrated LIN transceiver of the UJA1061 is a LIN 2.0 compliant transceiver. The
transceiver has the following features:
Fig 9. States LIN transceiver
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SAE J2602 compliant and compatible with LIN revision 1.3
Fail-safe LIN termination to BAT42 via dedicated RTLIN pin
Enhanced error handling and reporting of bus and TXD failures; these failures are
separately identified in the System Diagnosis register
power-on
Normal or Flash mode
Rev. 05 — 22 November 2007
AND LMC = 1
SBC enters
transmitter: ON/OFF (LTC)
RXDL: wake-up status
RTLIN: 75 A/OFF
RTLIN: ON/75 A
receiver: wake-up
RXDL: bitstream
transmitter: OFF
Fault-tolerant CAN/LIN fail-safe system basis chip
Off-line mode
Active mode
receiver: ON
Restart or Fail-safe mode
Stand-by, Start-up,
OR LMC = 0
SBC enters
TXDC(dom)
Fail-safe mode
SBC enters
001aad184
the CAN transmitter is
© NXP B.V. 2007 Nov 23. All rights reserved.
UJA1061
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