uja1061 NXP Semiconductors, uja1061 Datasheet - Page 39

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 14.
[1]
[2]
Table 15.
UJA1061_5
Product data sheet
Bit
15, 14
13
12
11
10 to 0
Bit
15 and 14
13
12
11 to 0
The Device Identification Control bit is cleared during power-up of the SBC, indicating that General Purpose register 0 is loaded with the
Device Identification Code. Any write access to General Purpose register 0 will set the DIC bit, regardless of the value written to DIC.
During power-up the General Purpose register 0 is loaded with a ‘Device Identification Code’ consisting of the SBC type and SBC
version, and the DIC bit is cleared.
General Purpose register 0 and General Purpose Feedback register 0 bit description
General Purpose register 1 and General Purpose Feedback register 1 bit description
Symbol
A1, A0
RRS
RO
DIC
GP0[10:0]
Symbol
A1, A0
RRS
RO
GP1[11:0]
6.13.11 General Purpose registers and General Purpose Feedback registers
The UJA1061 offers two 12-bit General Purpose registers (and accompanying General
Purpose Feedback registers) with no predefined bit definition. These registers can be
used by the microcontroller for advanced system diagnosis, or for storing critical system
status information outside the microcontroller. After Power-up General Purpose register 0
will contain a ‘Device Identification Code’ consisting of the SBC type and SBC version.
This code is available until it is overwritten by the microcontroller (as indicated by the DIC
bit).
Description
register address
Read Register Select
Read Only
Device Identification
Control
General Purpose bits
Description
register address
Read Register Select
Read Only
General Purpose bits
[1]
Rev. 05 — 22 November 2007
[2]
Value
10
1
0
1
0
1
0
1
0
Value
11
1
0
1
0
1
0
Function
select General Purpose Feedback register 0
read the General Purpose Feedback register 0
read the System Configuration Feedback register
read the register selected by RRS without writing to the
General Purpose register 0
read the register selected by RRS and write to the General
Purpose register 0
General Purpose register 0 contains user-defined bits
General Purpose register 0 contains the Device
Identification Code
user-defined
user-defined
Function
select General Purpose register 1
read the General Purpose Feedback register 1
read the Physical Layer Control Feedback register
read the register selected by RRS without writing to the
General Purpose register 1
read the register selected by RRS and write to the General
Purpose register 1
user-defined
user-defined
Fault-tolerant CAN/LIN fail-safe system basis chip
© NXP B.V. 2007 Nov 23. All rights reserved.
UJA1061
39 of 74