uja1061 NXP Semiconductors, uja1061 Datasheet - Page 9

• Manufacturer Part Number: uja1061
• Description: Low Speed Can/lin System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1061_5
Product data sheet
6.2.1 Start-up mode
6.2.2 Restart mode
6.2.3 Fail-safe mode
6.2.4 Normal mode
Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and
ground are connected for the first time. Start-up mode is also entered after any event that
results in a system reset. The reset source information is provided by the SBC to support
different software initialization cycles that depend on the reset event.
It is also possible to enter Start-up mode via a wake-up from Standby mode, Sleep mode
or Fail-safe mode. Such a wake-up can originate either from the CAN-bus, the LIN-bus or
from the local WAKE pin.
On entering Start-up mode a lengthened reset time t
either user-defined (via the RLC bit in the System Configuration register) or defaults to the
value as given in
LOW by the SBC.
When the reset time is completed (pin RSTN is released and goes HIGH) the watchdog
timer will wait for initialization. If the watchdog initialization is successful, the selected
operating mode (Normal mode or Flash mode) will be entered. Otherwise the Restart
mode will be entered.
The purpose of the Restart mode is to give the application a second chance to start up,
should the first attempt from Start-up mode fail. Entering Restart mode will always set the
reset lengthening time t
regardless of previous events.
If start-up from Restart mode is successful (the previous problems do not reoccur and
watchdog initialization is successful), then the selected operating mode will be entered.
From Restart mode this must be Normal mode. If problems persist or if V1 fails to start up,
then Fail-safe mode will be entered.
Severe fault situations will cause the SBC to enter Fail-safe mode. Fail-safe mode is also
entered if start-up from Restart mode fails. Fail-safe mode offers the lowest possible
system power consumption from the SBC and from the external components controlled by
the SBC.
A wake-up (via the CAN-bus, the LIN-bus or the WAKE pin) is needed to leave Fail-safe
mode. This is only possible if the on-chip oscillator is running correctly. The SBC restarts
from Fail-safe mode with a defined delay t
entering Start-up mode. Regulator V1 will restart and the reset lengthening time t
set to the higher value; see
Normal mode gives access to all SBC system resources, including CAN, LIN, INH/LIMP
and EN. Therefore in Normal mode the SBC watchdog runs in (programmable) Window
mode, for strictest software supervision. Whenever the watchdog is not properly served a
system reset is performed.
Interrupts from SBC to the host microcontroller are also monitored. A system reset is
performed if the host microcontroller does not respond within t
Section
Rev. 05 — 22 November 2007
RSTNL
6.13.12. During the reset lengthening time pin RSTN is held
Section
to the higher value to guarantee the maximum reset length,
Fault-tolerant CAN/LIN fail-safe system basis chip
6.5.1.
ret
, to guarantee a discharged V1 before
RSTNL
is observed. This reset time is
RSTN(INT)
© NXP B.V. 2007 Nov 23. All rights reserved.
UJA1061
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RSTNL
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