hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 110

• Manufacturer Part Number: hyb18t512160af-5
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

8.3.5
1. For all input signals the total input setup time and
2. For slow Slew Rate the total setup time might be
Table 57
Command / Address Slew Rate
(V/ns)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
1) For all input signals
2) For slow slewrate the total setup time might be negative (i.e. valid input signal will not have reached V
Data Sheet
input hold time required is calculated by adding the
data sheet value to the derating value respectively.
Example:
negative (i.e. a valid input signal will not have
reached
time of the rising clock) a valid signal is still required to complete the transistion and reach V
between the values listed in the next tables, the derating values may be obtained by linear interpolation. These values are
not subject to production test. They are verified only by design and characterisation.
V
Setup (
Derating Values for Input Setup and Hold Time (DDR2-667)
t
IH(ac)
IS
(total setup tine) =
/
V
IL(ac)
t
t
IS
IS
(total) =
) and Hold (
at the time of the rising clock)
t
IS
(base) + ∆
t
IS
CK, CK Differential Slew Rate
2.0 V/ns
∆
+150
+143
+133
+120
+100
+67
0
–5
–13
–22
–34
–60
–100
–168
–200
–325
–517
–1000
(base) + ∆
t
IS
t
IH
) Time Derating Tables
t
IS
and
∆
+94
+89
+83
+75
+45
+21
0
–14
–31
–54
–83
–125
–188
–292
–375
–500
–708
–1125
t
t
IS
IH
t
IH
(total) =
110
1.5 V/ns
∆
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
–4
–30
–70
–138
–170
–295
–487
–970
t
t
IS
IH
(base) + ∆
a valid input signal is still required to complete the
transition and reach
in between the values listed in the next tables, the
derating values may be obtained by linear
interpolation. These values are not subject to
production test. They are verified only by design
and characterization.
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
∆
+124
+119
+113
+105
+75
+51
+30
+16
–1
–24
–53
–95
–158
–262
–345
–470
–678
–1095
t
IH
t
IH
AC Timing Measurement Conditions
1.0 V/ns
∆
+210
+203
+193
+180
+160
+127
+60
+55
+47
+38
+26
0
–40
–108
–140
–265
–457
–940
t
IS
V
512-Mbit DDR2 SDRAM
IH(ac)
IH(ac)
∆
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
–23
–65
–128
–232
–315
–440
–648
–1065
/
t
IH
09112003-SDM9-IQ3P
V
/ V
IL(ac)
IL(ac)
Rev. 1.3, 2005-01
. For Slew Rates
IH(ac)
. For slew rates in
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
/ V
IL(ac)
Note
1)2)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
at the