hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 32

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hyb18t512160af-5

Manufacturer Part Number
hyb18t512160af-5
Description
512-mbit Ddr2 Sdram
Manufacturer
Infineon Technologies Corporation
Datasheet
Table 9
Field
A13
Qoff
RDQS
DQS
OCD
Program
AL
R
DIC
DLL
1) w = write only register bits
2) optional for DDR2-400/533 & 667
Data Sheet
TT
Bits
13
12
11
10
[9:7]
[5:3]
2,6
1
0
Extended Mode Register Definition (BA[2:0] = 001B)
Type
w
1)
Description
Address Bus[13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0
Output Disable
0
1
Read Data Strobe Output (RDQS, RDQS)
0
1
Complement Data Strobe (DQS Output)
0
1
Off-Chip Driver Calibration Program
000
001
010
100
111
Additive Latency
Note: All other bit combinations are illegal.
000
001
010
011
100
101
Nominal Termination Resistance of ODT
00
01
10
11
Off-chip Driver Impedance Control
0
1
DLL Enable
0
1
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
A13, Address bit 13
QOff, Output buffers enabled
QOff, Output buffers disabled
RDQS, Disable
RDQS, Enable
DQS, Enable
DQS, Disable
OCD, OCD calibration mode exit, maintain setting
OCD, Drive (1)
OCD, Drive (0)
OCD, Adjust mode
OCD, OCD calibration default
AL, 0
AL, 1
AL, 2
AL, 3
AL, 4
AL, 5
RTT, ∞ (ODT disabled)
RTT, 75 Ohm
RTT, 150 Ohm
RTT, 50 Ohm
DIC, Full (Driver Size = 100%)
DIC, Reduced
DLL, Enable
DLL, Disable
2)
32
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
09112003-SDM9-IQ3P
Rev. 1.3, 2005-01

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