hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 80

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hyb18t512160af-5

Manufacturer Part Number
hyb18t512160af-5
Description
512-mbit Ddr2 Sdram
Manufacturer
Infineon Technologies Corporation
Datasheet
Table 30
Symbol
V
V
V
V
V
1)
2)
3)
4) The value of
5) The value of
Figure 65
Data Sheet
IN(dc)
ID(dc)
ID(ac)
IX(ac)
OX(ac)
V
V
V
V
V
IN(dc)
ID(dc)
ID(ac)
DDQ
DDQ
.
.
V
V
specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
specifies the input differential voltage
specifies the input differential voltage
IX(ac)
OX(ac)
Parameter
DC input signal voltage
DC differential input voltage
AC differential input voltage
AC differential cross point input
voltage
AC differential cross point output
voltage
Differential DC and AC Input and Output Logic Levels
Differential DC and AC Input and Output Logic Levels Diagram
indicates the voltage at which differential input signals must cross.
V
V
indicates the voltage at which differential input signals must cross.
OX(ac)
IX(ac)
VTR
VCP
is expected to equal 0.5 ×
is expected to equal 0.5 ×
VID
V
V
TR
TR
V
V
Crossing Point
DDQ
DDQ
V
V
CP
CP
of the transmitting device and
of the transmitting device and
Min.
–0.3
0.25
0.5
0.5 ×
0.5 ×
required for switching. The minimum value is equal to
required for switching. The minimum value is equal to
80
V
V
DDQ
DDQ
VIX or VOX
– 0.175
– 0.125
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
SSTL18_3
Max.
V
V
V
0.5 ×
0.5 ×
DDQ
DDQ
DDQ
V
V
IX(ac)
OX(ac)
AC & DC Operating Conditions
+ 0.3
+ 0.6
+ 0.6
V
V
DDQ
DDQ
is expected to track variations in
512-Mbit DDR2 SDRAM
is expected to track variations in
+ 0.175
+ 0.125
VDDQ
VSSQ
09112003-SDM9-IQ3P
Rev. 1.3, 2005-01
Unit
V
V
V
V
V
IH(dc)
IH(ac)
Note
1)
2)
3)
4)
5)
V
V
IL(dc)
IL(ac)
.
.

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