hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 19

• Manufacturer Part Number: hyb18t512160af-5
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Table 4
Ball#/Pin#
Not Connected ×16 organization
A2, E2, L1, R3,
R7, R8
Other Pins ×4/×8 organizations
F9
Other Pins ×16 organization
K9
Table 5
Abbreviation
I
O
I/O
AI
PWR
GND
NC
Table 6
Abbreviation
SSTL
LV-CMOS
CMOS
OD
Data Sheet
Pin Configuration of DDR SDRAM
Abbreviations for Pin Type
Abbreviations for Buffer Type
Name
NC
ODT
ODT
Pin
Type
NC
I
I
Description
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
Buffer
Type
–
SSTL
SSTL
Function
Not Connected
On-Die Termination Control
Note: ODT (registered HIGH) enables termination resistance
On-Die Termination Control
internal to the DDR2 SDRAM. When enabled, ODT is
applied to each DQ, DQS, DQS and DM signal for
DQ, DQS, DQS, RDQS, RDQS and DM for
configurations. For
each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM
signal. The ODT pin will be ignored if the Extended Mode
Register (EMRS(1)) is programmed to disable ODT.
19
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
Pin Configuration and Block Diagrams
×
16 configuration ODT is applied to
512-Mbit DDR2 SDRAM
09112003-SDM9-IQ3P
Rev. 1.3, 2005-01
×
8
×
4 and