hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 39

• Manufacturer Part Number: hyb18t512160af-5
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

3.13
On-Die Termination (ODT) is a new feature on DDR2
components that allows a DRAM to turn on/off termi-
nation resistance for each DQ, DQS, DQS, DM for ×4
and DQ, DQS, DQS, DM, RDQS (DM/RDQS share the
same pin) and RDQS for ×8 configuration via the ODT
control pin. DQS and RDQS are only terminated when
enabled by EMR(1).
For ×16 configuration ODT is applied to each DQ,
UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via
Figure 12
Switch sw1, sw2 or sw3 are enabled by the ODT pin.
Selection between sw1, sw2 or sw3 is determined by
“Rtt (nominal)” in EMRS(1) address bits A6 & A2.
Data Sheet
On-Die Termination (ODT)
Functional Representation of ODT
DRAM
Buffer
Input
VDDQ
VSSQ
xx
xx
Rval1
Rval1
sw1
sw1
39
VDDQ
VSSQ
xx
xx
the ODT control pin. UDQS and LDQS are terminated
only when enabled in the EMRS(1) by address bit
A10 = 0.
The ODT feature is designed to improve signal integrity
of the memory channel by allowing the DRAM
controller to independently turn on/off termination resis-
tance for any or all DRAM devices. The ODT function
can be used for all active and standby modes. ODT is
turned off and not supported in Self-Refresh mode.
Target: Rval1 = Rval2 = Rval3 = 2 × Rtt
The ODT pin will be ignored if the Extended Mode
Register (EMRS(1)) is programmed to disable ODT.
Rval2
sw2
Rval2
sw2
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
VDDQ
VSSQ
xx
xx
Rval3
sw3
Rval3
sw3
ODT_funct2
Input
Pin
512-Mbit DDR2 SDRAM
Functional Description
09112003-SDM9-IQ3P
Rev. 1.3, 2005-01