hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 111

• Manufacturer Part Number: hyb18t512160af-5
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Table 58
Command / Address Slew Rate
(V/ns)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
1) For all input signals
2) For slow slewrate the total setup time might be negative (i.e. valid input signal will not have reached V
Data Sheet
time of the rising clock) a valid signal is still required to complete the transistion and reach V
between the values listed in the next tables, the derating values may be obtained by linear interpolation. These values are
not subject to production test. They are verified only by design and characterisation.
Derating Values for Input Setup and Hold Time (DDR2-400 & DDR2-533)
t
IS
(total) =
t
IS
(base) + ∆
CK, CK Differential Slew Rate
2.0 V/ns
∆
+187
+179
+167
+150
+125
+83
0
–11
–25
–43
–67
–110
–175
–285
–350
–525
–800
–1450
t
IS
t
IS
and
∆
+94
+89
+83
+75
+45
+21
0
–14
–31
–54
–83
–125
–188
–292
–375
–500
–708
–1125
t
IH
t
IH
(total) =
111
1.5 V/ns
∆
+217
+209
+197
+180
+155
+113
+30
+19
+5
–13
–37
–80
–145
–255
–320
–495
–770
–1420
t
t
IS
IH
(base) + ∆
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
∆
+124
+119
+113
+105
+75
+51
+30
+16
–1
–24
–53
–95
–158
–262
–345
–470
–678
–1095
t
IH
t
IH
AC Timing Measurement Conditions
1.0 V/ns
∆
+247
+239
+227
+210
+185
+143
+60
+49
+35
+17
–7
–50
–115
–225
–290
–465
–740
–1390
t
IS
512-Mbit DDR2 SDRAM
IH(ac)
∆
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
–23
–65
–128
–232
–315
–440
–648
–1065
t
IH
09112003-SDM9-IQ3P
/ V
IL(ac)
Rev. 1.3, 2005-01
IH(ac)
. For slew rates in
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
/ V
IL(ac)
Note
1)2)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
at the