hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 60

• Manufacturer Part Number: hyb18t512160af-5
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Figure 43
RL = 6, (AL = 2, CL = 4), BL = 4,
Figure 44
RL = 4, (AL = 0, CL = 4), BL = 8,
3.22.2
Minimum Write to Precharge command spacing to the
same bank = WL + BL/2 +
must be satisfied from the completion of the last burst
write cycle until the Precharge command can be
issued. This delay is known as a write recovery time
(
Data Sheet
t
WR
DQS,
DQS
CK, CK
CMD
C M D
D Q S ,
D Q S
) referenced from the completion of the burst write
DQ
C K , C K
D Q
first 4-bit prefetch
Posted CAS
T0
R E A D A
T0
READ A
Read Operation Followed by Precharge Example 4
Read Operation Followed by Precharge Example 5
Write followed by Precharge
AL + BL/2 clocks
AL = 2
T1
T1
NOP
N O P
A L + B L /2 clks + 1
>=tRAS
RL = 6
C L = 4
R L = 4
t
second 4-bit prefetch
WR
> = tR A S
. For write cycles, a delay
T2
T2
t
t
N O P
NOP
RTP
RTP
>=tRC
≤ 2 CKs
> 2 CKs
>=tRTP
T3
T3
CL = 4
N O P
NOP
> = tR T P
Precharge
T4
T4
60
N O P
Dout A0
A
to the Precharge command. No Precharge command
should be issued prior to the
SDRAM does not support any burst interrupt by a
Precharge command.
parameter (see
value WR in the MR.
Dout A1
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
P re ch a rg e
T5
T5
NOP
Dout A2
tRP
CL = 4
Dout A3
Chapter
T6
T6
N O P
NOP
Dout A0
Dout A4
tR P
512-Mbit DDR2 SDRAM
7) and is not the programmed
Dout A1
Dout A5
t
WR
T7
T7
Functional Description
N O P
NOP
is an analog timing
Dout A2
Dout A6
09112003-SDM9-IQ3P
t
WR
Dout A3
Dout A7
Rev. 1.3, 2005-01
delay, as DDR2
T8
B a n k A
A ctiva te
T8
Bank A
Activate
BR-P404(8)
BR-P624