hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 58

• Manufacturer Part Number: hyb18t512160af-5
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

3.22
The Precharge Command is used to precharge or close
a bank that has been activated. The Precharge
Command is triggered when CS, RAS and WE are
LOW and CAS is HIGH at the rising edge of the clock.
Table 17
A10
0
0
0
0
1
Note: The bank address assignment is the same for activating and precharging a specific bank.
3.22.1
The following rules apply as long as the
parameter - Internal Read to Precharge Command
delay time - is less or equal two clocks, which is the
case for operating frequencies less or equal 266 MHz
(DDR2 400 and 533 speed sorts).
Minimum Read to Precharge command spacing to the
same bank = AL + BL/2 clocks. For the earliest possible
precharge, the Precharge command may be issued on
the rising edge which is “Additive Latency (AL) + BL/2
clocks” after a Read Command, as long as the
minimum
Figure 40
RL = 4 (AL = 1, CL = 3), BL = 4,
Data Sheet
DQS,
DQS
CK, CK
CMD
DQ
t
RAS
Posted CAS
T0
READ A
Precharge Command
Bank Selection for Precharge by Address Bits
Read Followed by a Precharge
Read Operation Followed by Precharge Example 1
timing is satisfied.
AL = 1
T1
AL + BL/2 clks
BA1
0
0
1
1
Don’t Care
NOP
>=tRAS
RL = 4
>=tRTP
CL = 3
T2
t
NOP
RTP
>=tRC
≤ 2 CKs
Precharge
T3
t
RTP
BA0
0
1
0
1
Don’t Care
timing
T4
58
NOP
Dout A0
tRP
The Pre-charge Command can be used to precharge
each bank independently or all banks simultaneously. 3
address bits A10, BA[1:0] are used to define which
bank to precharge when the command is issued.
The term (t
frequencies less or equal 266 MHz (DDR2-400 and
DDR2-533 product speed sorts). The term (t
is one clock for frequencies higher then 266 MHz
(DDR2-667 speed sort).
A new bank active command may be issued to the
same bank if the following two conditions are satisfied
simultaneously:
1. The RAS precharge time (
2. The RAS cycle time (
CL = 3
Dout A1
from the clock at which the precharge begins.
activation has been satisfied.
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
T5
NOP
Dout A2
RTP
Dout A3
Precharge Bank(s)
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
all banks
- 2×t
T6
Bank A
Activate
CK
t
512-Mbit DDR2 SDRAM
RC.MIN
) is 0 clocks for operating
T7
t
NOP
Functional Description
) from the previous bank
RP
09112003-SDM9-IQ3P
) has been satisfied
Rev. 1.3, 2005-01
T8
NOP
BR-P413
RTP
- 2×t
CK
)