hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 53

• Manufacturer Part Number: hyb18t512160af-5
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

3.19
The Write command is initiated by having CS, CAS and
WE LOW while holding RAS HIGH at the rising edge of
the clock. The address inputs determine the starting
column address. Write latency (WL) is defined by a
read latency (RL) minus one and is equal to (AL + CL –
(preamble) a time
bit of the burst cycle must be applied to the DQ pins at
the first rising edge of the DQS following the preamble.
The
cycles. The subsequent burst bit data are issued on
Figure 30
Figure 31
RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4
Data Sheet
1). A data strobe signal (DQS) has to be driven LOW
DQS,
DQS
CK, CK
CMD
DQ
t
DQSS
Posted CAS
WRITE A
T0
specification must be satisfied for write
Write Command
Basic Write Timing
Write Operation Example 1
DQS,
DQS
t
WPRE
T1
NOP
WL = RL-1 = 4
prior to the WL. The first data
T2
NOP
t
DS
T3
t
NOP
WPRE
Din
t
DQSH
DQS
DQS
T4
DIN A0
NOP
53
Din
<= t DQSS
t
successive edges of the DQS until the burst length is
completed. When the burst has finished, any additional
data supplied to the DQ pins will be ignored. The DQ
signal is ignored after the burst write operation is
complete. The time from the completion of the burst
write to bank precharge is named “write recovery time”
(
the memory array.
(see
WR in the MRS.
DQSL
t
DIN A1
WR
t
DH
) and is the time needed to store the write data into
Chapter
T5
Din
DIN A2
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
NOP
DIN A3
Din
5) and is not the programmed value for
T6
t
NOP
WPST
t
WR
Completion of
the Burst Write
is an analog timing parameter
512-Mbit DDR2 SDRAM
tWR
T7
NOP
Functional Description
09112003-SDM9-IQ3P
Rev. 1.3, 2005-01
Precharge
T9
BW543