hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 49

• Manufacturer Part Number: hyb18t512160af-5
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

3.17
Burst mode operation is used to provide a constant flow
of data to memory locations (write cycle), or from
memory locations (read cycle). The parameters that
define how the burst mode will operate are burst
sequence and burst length. The DDR2 SDRAM
supports 4 bit and 8 bit burst modes only. For 8 bit burst
mode, full interleave address ordering is supported,
however, sequential address ordering is nibble based
for ease of implementation. The burst length is
programmable and defined by the addresses A[2:0] of
Table 16
Burst Length
4
8
Note:
1. PageSize and Length is a function of I/O organization:
2. Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR or DDR
Data Sheet
128Mb x 4 organization (CA[9:0], CA11); Page Size = 1 kByte; Page Length = 2048
64Mb x 8 organization (CA[9:0]); Page Size = 1 kByte; Page Length = 1024
32Mb x 16 organization (CA[9:0]); Page Size = 2 kByte; Page Length = 1024
components
Burst Mode Operation
Burst Length and Sequence
Starting Address
x 0 0
x 0 1
x 1 0
x 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
(A2 A1 A0)
49
Sequential Addressing
(decimal)
0, 1, 2, 3
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
5, 6, 7, 4, 1, 2, 3, 0
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
the MR. The burst type, either sequential or
interleaved, is programmable and defined by the
address bit 3 (A3) of the MR. Seamless burst read or
write operations are supported. Interruption of a burst
read or write operation is prohibited, when burst length
= 4 is programmed. For burst interruption of a read or
write burst when burst length = 8 is used, see
Chapter
on DDR2 SDRAM devices.
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
3.21. A Burst Stop command is not supported
512-Mbit DDR2 SDRAM
Interleave Addressing
(decimal)
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Functional Description
09112003-SDM9-IQ3P
Rev. 1.3, 2005-01