MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 114
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 3 Port Integration Module (PIM9NE64V1)
Read:Anytime.
Write:Anytime.
This register configures each port T pin as either input or output.
The standard TIM module forces the I/O state to be an output for each port pin associated with an enabled
output compare. When the pin is configured as an output compare the corresponding data direction register
(DDRT) bits do not have any effect on the I/O direction of the pin, and will maintain their previously
latched value. The DDRT bits revert to controlling the I/O direction of a pin when the associated timer
output compare is disabled. If a pin is being used as a timer input capture, the DDRT remains in control of
the pin’s I/O direction and the timer monitors the state of the pin.
DDRT[7:4] — Data Direction Port T
3.3.2.1.4
Read:Anytime.
Write:Anytime.
This register configures the drive strength of each port T output pin as either full or reduced. If the port is
used as input this bit is ignored.
RDRT[7:4] — Reduced Drive Port T
114
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on
PTT or PTIT registers, when changing the DDRT register.
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
Module Base + $3
Reset:
Read:
Write:
Reduced Drive Register (RDRT)
RDRT7
Bit 7
0
= Reserved or unimplemented
RDRT6
Figure 3-5. Port T Reduced Drive Register (RDRT)
6
0
MC9S12NE64 Data Sheet, Rev. 1.1
RDRT5
5
0
RDRT4
4
0
—
3
0
—
2
0
—
1
0
Freescale Semiconductor
Bit 0
—
0
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