MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 463
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MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Figure 17-13
occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.
Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being
connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this
case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Because this is
not a probable situation, the protocol does not prevent this conflict from happening.
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE
BDM commands. This provides backwards compatibility with the existing POD devices which are not
able to execute the hardware handshake protocol. It also allows for new POD devices, that support the
hardware handshake protocol, to freely communicate with the target device. If desired, without the need
for waiting for the ACK pulse.
Freescale Semiconductor
(TARGET MCU)
BKGD PIN
DRIVES SYNC
TARGET MCU
TO BKGD PIN
BDM CLOCK
DRIVES TO
BKGD PIN
BKGD PIN
HOST
shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could
This information is being provided so that the MCU integrator will be aware
that such a conflict could eventually occur.
READ_BYTE
HOST
Figure 17-12. ACK Abort Procedure at the Command Level
AND STARTS TO EXECUTES
READ_BYTE CMD IS ABORTED
Figure 17-13. ACK Pulse and SYNC Request Conflict
THE READ_BYTE CMD
MEMORY ADDRESS
TARGET
BY THE SYNC REQUEST
HOST SYNC REQUEST PULSE
BDM DECODE
ACK PULSE
16 CYCLES
(OUT OF SCALE)
MC9S12NE64 Data Sheet, Rev. 1.1
HOST AND
TARGET DRIVE
TO BKGD PIN
AT LEAST 128 CYCLES
NOTE
ELECTRICAL CONFLICT
HIGH-IMPEDANCE
HOST
SYNC RESPONSE
FROM THE TARGET
(OUT OF SCALE)
READ_STATUS
TARGET
NEW BDM COMMAND
NEW BDM COMMAND
HOST
Functional Description
SPEEDUP PULSE
TARGET
463
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