MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 250
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 8 Serial Communication Interface (SCIV3)
indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register
2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
8.4.5.3
The receiver samples the RXD pin at the RT clock rate. The RT clock is an internal signal with a frequency
16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see
re-synchronized:
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 8-14
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
250
RT CLOCK COUNT
RESET RT CLOCK
•
•
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
RT CLOCK
SAMPLES
summarizes the results of the start bit verification samples.
RXD
Data Sampling
1
RT3, RT5, and RT7 Samples
1
1
1
000
001
010
011
100
101
110
111
1
QUALIFICATION
Figure 8-15. Receiver Data Sampling
1
START BIT
Table 8-14. Start Bit Verification
MC9S12NE64 Data Sheet, Rev. 1.1
1
1
0
0
VERIFICATION
Start Bit Verification
START BIT
0
Yes
Yes
Yes
Yes
No
No
No
No
0
START BIT
SAMPLING
0
DATA
0
0
Noise Flag
Figure
0
1
1
0
1
0
0
0
8-15) is
Freescale Semiconductor
LSB
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