MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 131
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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3.3.2.6
3.3.2.6.1
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The EPHY LED drive takes precedence over general-purpose I/O function if the EPHYCTL0 LEDEN bit
is enabled. With the LEDEN bit set, PTL[4:0] become COLLED, DUPLED, SPDLED, LNKLED, and
ACTLED. Refer to EPHY block description chapter for more detail.
3.3.2.6.2
Read:Anytime.
Write:Never, writes to this register have no effect.
This register always reads back the status of the associated pins. This also can be used to detect overload
or short circuit conditions on output pins.
Freescale Semiconductor
Module Base + $28
Module Base + $29
Reset:
Reset:
Read:
Read:
Write:
Write:
PHY
Port L Registers
I/O Register (PTL)
Input Register (PTIL)
Bit 7
Bit 7
—
—
0
0
= Reserved or unimplemented
= Reserved or unimplemented
PTIL6
PTL6
—
6
0
6
Figure 3-40. Port L Input Register (PTIL)
Figure 3-39. Port L I/O Register (PTL)
MC9S12NE64 Data Sheet, Rev. 1.1
PTIL5
PTL5
—
5
0
5
COLLED
PTIL4
PTL4
—
4
0
4
DUPLED
PTIL3
PTL3
—
3
0
3
SPDLED
PTIL2
PTL2
—
2
0
2
Memory Map and Register Descriptions
LNKLED
PTIL1
PTL1
—
1
0
1
ACTLED
PTIL0
PTL0
Bit 0
Bit 0
—
0
131
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