MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 258
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MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 8 Serial Communication Interface (SCIV3)
Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control
register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting
the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled
(TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as
an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation.
8.4.7
In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the
SCI
Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1
(SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC
bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled
(TE = 1 and RE = 1).
8.5
This section describes the interrupt originated by the SCI block.The MCU must service the interrupt
requests.
8.5.1
The SCI only originates interrupt requests. The following is a description of how the SCI makes a request
and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are
258
.
Table 8-17
Interrupts
Loop Operation
Description of Interrupt Operation
Interrupt
RDRF
TDRE
IDLE
OR
TC
lists the five interrupt sources of the SCI.
SCISR1[7]
SCISR1[6]
SCISR1[5]
SCISR1[3]
SCISR1[4]
Figure 8-25. Loop Operation (LOOPS = 1, RSRC = 0)
Source
TRANSMITTER
RECEIVER
Table 8-17. SCI Interrupt Sources
MC9S12NE64 Data Sheet, Rev. 1.1
Local Enable
TCIE
RIE
ILIE
TIE
Active high level. Indicates that a byte was
transferred from SCIDRH/L to the transmit
shift register.
Active high level. Indicates that a transmit is
complete.
Active high level. The RDRF interrupt indicates
that received data is available in the SCI data
register.
Active high level. This interrupt indicates that
an overrun condition has occurred.
Active high level. Indicates that receiver input
has become idle.
RXD
TXD
Description
Freescale Semiconductor
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