MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 310
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 11 Ethernet Media Access Controller (EMACV1)
11.2.6
MII_RXD[3:0] is a receive nibble of data to be transferred from the PHY to the EMAC. The nibble is
synchronized to the rising edge of MII_RXCLK. When MII_RXDV is asserted, the EMAC accepts the
MII_RXD[3:0], and at all other times, MII_RXD[3:0] is ignored. MII_RXD[0] is the least significant bit.
Table 11-2
the specific indication provided by each code. A false carrier indication is ignored by the EMAC.
11.2.7
When this input signal is asserted, the PHY is indicating that a valid nibble is present on the MII. This
signal remains asserted from the first recovered nibble of the frame through the last nibble. Assertion of
MII_RXDV must start no later than the start frame delimiter (SFD).
11.2.8
When this input signal and MII_RXDV are asserted, the PHY is indicating that a media error has been
detected during the transmission of the current frame. At all other times, MII_RXER is ignored. This
signal transitions synchronously with MII_RXCLK.
11.2.9
This input signal is asserted when the transmit or receive medium is in a non-idle state. When de-asserted,
this signal indicates that the medium is in an idle state and a transmission can start. In the event of a
collision, MII_CRS remains asserted through the duration of the collision. In full-duplex mode, this signal
is undefined. This signal is not required to transition synchronously with MII_TXCLK or MII_RXCLK.
11.2.10 MII_COL — MII Collision
This input signal is asserted upon detection of a collision, and remains asserted through the duration of the
collision. In full-duplex mode, this signal is undefined. This signal is not required to transition
synchronously with MII_TXCLK or MII_RXCLK.
310
MII_RXD[3:0] — MII Receive Data
summarizes the permissible encoding of MII_RXD, MII_RXDV, and MII_RXER, as well as
MII_RXDV — MII Receive Data Valid
MII_RXER — MII Receive Error
MII_CRS — MII Carrier Sense
MII_RXDV
Table 11-2. Permissible Encoding of MII_RXD, MII_RXDV, and MII_RXER
0
0
0
0
0
1
1
MII_RXER
0
1
1
1
1
0
1
MC9S12NE64 Data Sheet, Rev. 1.1
0000 through 1111
0001 through 1101
0000 through 1111
0000 through 1111
MII_RXD[3:0]
0000
1110
1111
Data reception with errors
Normal data reception
Normal interframe
Normal interframe
False carrier
Indication
Reserved
Reserved
Freescale Semiconductor
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