MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 74

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 2 64 Kbyte Flash Module (S12FTS64KV3)
2.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.
2.3.2.2
The FSEC register holds all bits associated with the security of the MCU and Flash module.
74
FDIV[5:0]
FDIVLD
PRDIV8
RESERVED2
RESERVED3
RESERVED4
Reset
Field
Register
5-0
7
6
Name
W
R
FDIVLD
Clock Divider Loaded.
0 Register has not been written.
1 Register has been written to since the last reset.
Enable Prescalar by 8
0 The oscillator clock is directly fed into the clock divider
1 The oscillator clock is divided by 8 before feeding into the clock divider.
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to
FCLKDIV Register”
Flash Clock Divider Register (FCLKDIV)
Flash Security Register (FSEC)
7
0
W
W
W
R
R
R
= Unimplemented or Reserved
PRDIV8
Bit 7
0
0
0
6
0
Figure 2-3. FTS64K Register Summary (continued)
Figure 2-4. Flash Clock Divider Register (FCLKDIV)
for more information.
.
= Unimplemented or Reserved
Table 2-4. FCLKDIV Field Descriptions
6
0
0
0
FDIV5
MC9S12NE64 Data Sheet, Rev. 1.1
5
0
5
0
0
0
FDIV4
4
0
Description
4
0
0
0
.
FDIV3
3
0
3
0
0
0
FDIV2
2
0
2
0
0
0
Section 2.4.1.1, “Writing the
Freescale Semiconductor
FDIV1
1
0
1
0
0
0
Bit 0
FDIV0
0
0
0
0
0