MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 311
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MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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11.2.11 MII_MDC — MII Management Data Clock
This output signal provides a timing reference to the PHY for data transfers on the MII_MDIO signal.
MII_MDC is aperiodic and has no maximum high or low times. The maximum clock frequency is
2.5 MHz, regardless of the nominal period of MII_TXCLK and MII_RXCLK.
11.2.12 MII_MDIO — MII Management Data Input/Output
This bidirectional signal transfers control/status information between the PHY and EMAC. Control
information is driven by the EMAC synchronously with respect to MII_MDC and is sampled
synchronously by the PHY. Status information is driven by the PHY synchronously with respect to
MII_MDC and is sampled synchronously by the EMAC.
11.3
This section provides a detailed description of all registers accessible in the EMAC.
11.3.1
Table 11-3
the memory space. The register address results from the addition of base address and address offset. The
base address is determined at the MCU level and is given in the device user guide. The address offset is
defined at the module level and is provided in
Freescale Semiconductor
Memory Map and Register Descriptions
Module Memory Map
gives an overview of all registers in the EMAC memory map. The EMAC occupies 48 bytes in
Address
$__0C
$__0D
Offset
$__00
$__01
$__02
$__03
$__04
$__05
$__06
$__07
$__08
$__09
$__0A
$__0B
$__0E
$__0F
$__10
$__11
Table 11-3. EMAC Module Memory Map
MII Management Register Address (MRADR)
PAUSE Timer Value and Counter (PTIME)
MII Management PHY Address (MPADR)
MC9S12NE64 Data Sheet, Rev. 1.1
Receive Control and Status (RXCTS)
Transmit Control and Status (TXCTS)
Programmable Ethertype (ETYPE)
Network Control (NETCTL)
Ethertype Control (ETCTL)
Software Reset (SWRST)
Interrupt Event (IEVENT)
Interrupt Mask (IMASK)
Table
Reserved
Reserved
11-3.
Use
Memory Map and Register Descriptions
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
311
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