MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 148
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MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 4 Clocks and Reset Generator (CRGV4)
4.3.2.4
This register provides CRG status bits and flags.
Read: anytime
Write: refer to each bit for individual write conditions
148
1. PORF is set to 1 when a power-on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset.
LOCKIF
TRACK
Reset
PORF
LOCK
Field
LVRF
RTIF
7
6
5
4
3
2
W
R
RTIF
Real-Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
Power-on Reset Flag — PORF is set to 1 when a power-on reset occurs. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 Power-on reset has not occurred.
1 Power-on reset has occurred.
Low-Voltage Reset Flag — If low voltage reset feature is not available (see the device overview chapter), LVRF
always reads 0. LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1.
Writing a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.If enabled (LOCKIE = 1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
Lock Status Bit — LOCK reflects the current state of PLL lock condition. This bit is cleared in self-clock mode.
Writes have no effect.
0 PLL VCO is not within the desired tolerance of the target frequency.
1 PLL VCO is within the desired tolerance of the target frequency.
Track Status Bit — TRACK reflects the current state of PLL track condition. This bit is cleared in self-clock mode.
Writes have no effect.
0 Acquisition mode status.
1 Tracking mode status.
CRG Flags Register (CRGFLG)
0
7
= Unimplemented or Reserved
Note 1
PORF
6
Figure 4-7. CRG Flag Register (CRGFLG)
Table 4-2. CRGFLG Field Descriptions
Note 2
LVRF
MC9S12NE64 Data Sheet, Rev. 1.1
5
LOCKIF
0
4
Description
LOCK
0
3
TRACK
0
2
Freescale Semiconductor
SCMIF
0
1
SCM
0
0
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