MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 350
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 12 Ethernet Physical Transceiver (EPHYV2)
12.2.4
Ethernet twisted-pair input pin. This pin is high-impedance out of reset.
12.2.5
Connect a 1.0% external resistor, RBIAS (see Electrical Characteristics chapter), between the
PHY_RBIAS pin and analog ground. Place this resistor as near to the chip pin as possible. Stray
capacitance must be kept to less than 10 pF (>50 pF will cause instability). No high-speed signals are
permitted in the region of RBIAS.
12.2.6
Power is supplied to the EPHY receiver through PHY_VDDRX and PHY_VSSRX. This 2.5 V supply is
derived from the internal voltage regulator. There is no static load on those pins allowed. The internal
voltage regulator is turned off, if V
12.2.7
External power is supplied to the EPHY transmitter through PHY_VDDTX and PHY_VSSTX. This 2.5 V
supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The
internal voltage regulator is turned off, if V
12.2.8
Power is supplied to the EPHY PLLs through PHY_VDDA and PHY_VSSA. This 2.5 V supply is derived
from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage
regulator is turned off, if V
12.2.9
Flashes in half-duplex mode when a collision occurs on the network if EPHYCTL0 LEDEN bit is set.
12.2.10 DUPLED — Duplex LED
Indicates the duplex of the link, which can be full-duplex or half-duplex if EPHYCTL0 LEDEN bit is set.
12.2.11 SPDLED — Speed LED
Indicates the speed of a link, which can be 10 Mbps or 100 Mbps if EPHYCTL0 LEDEN bit is set.
12.2.12 LNKLED — Link LED
Indicates whether a link is established with another network device if EPHYCTL0 LEDEN bit is set.
350
PHY_RXN — EPHY Twisted Pair Input –
PHY_RBIAS — EPHY Bias Control Resistor
PHY_VDDRX, PHY_VSSRX — Power Supply Pins for EPHY Receiver
PHY_VDDTX, PHY_VSSTX — Power Supply Pins for EPHY
Transmitter
PHY_VDDA, PHY_VSSA — Power Supply Pins for EPHY Analog
COLLED — Collision LED
DDR
is tied to ground.
DDR
MC9S12NE64 Data Sheet, Rev. 1.1
is tied to ground.
DDR
is tied to ground.
Freescale Semiconductor
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