MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 69
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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HCS12 core PPAGE register is used to map the logical middle page ranging from address 0x8000 to
0xBFFF to any physical 16 Kbyte page in the Flash memory. By placing 0x3E or 0x3F in the HCS12 Core
PPAGE register, the associated 16 Kbyte pages appear twice in the MCU memory map.
The FPROT register, described in
globally protect a Flash block. However, three separate memory regions, one growing upward from the
first address in the next-to-last page in the Flash block (called the lower region), one growing downward
from the last address in the last page in the Flash block (called the higher region), and the remaining
addresses in the Flash block, can be activated for protection. The Flash locations of these protectable
regions are shown in
because it covers the vector space. The lower address region can be used for EEPROM emulation in an
MCU without an EEPROM module because it can remain unprotected while the remaining addresses are
protected from program or erase.
Security information that allows the MCU to restrict access to the Flash module is stored in the Flash
configuration field, described in
Freescale Semiconductor
0xFF08 - 0xFF0C
0xFF00 - 0xFF07
Unpaged Flash
Address
0xFF0D
0xFF0E
0xFF0F
Table
2-2. The higher address region is mainly targeted to hold the boot loader code
Table
Paged Flash Address
Section 2.3.2.5, “Flash Protection Register
Table 2-1. Flash Configuration Field
0xBF08-0xBF0C
0xBF00-0xBF07
(PPAGE 0x3F)
MC9S12NE64 Data Sheet, Rev. 1.1
2-1.
0xBF0D
0xBF0E
0xBF0F
(bytes)
Size
8
5
1
1
1
Refer to
Refer to
Refer to
Refer to Section
Protection Register
“Unsecuring the MCU using
Backdoor Comparison Key
Security Register
Control Register
Backdoor Key
Flash Nonvolatile byte
Flash Protection byte
Flash Security byte
Section 2.3.2.5, “Flash
Section 2.3.2.9, “Flash
Section 2.3.2.2, “Flash
Description
Memory Map and Register Definition
Reserved
(FPROT)”, can be set to
Section 2.6.1,
Access”
(FCTL)”
(FSEC)”
(FPROT)”
69
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