MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 333
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MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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While the frame is being generated by the transmitting network node, the CRC value is simultaneously
being calculated. The 32 bits of the CRC value are placed in the FCS field while the frame is sent. The X
coefficient of the CRC polynomial is sent as the first bit of the field and the X
The CRC is calculated again by the receiving network node while the frame is read in. The result of this
second calculation is compared with the value sent in the FCS field by the originating network node. If the
two values are identical, the receiving network node is provided with a high level of assurance that no
errors have occurred during transmission over the network.
11.4.1.6 End-of-Frame Delimiter
The end-of-frame (EOF) delimiter is indicated by the de-assertion of the MII_TXEN signal for data on
MII_TXD. This informs the PHY to send a special EOF symbol on the Ethernet. For data on the MII_RXD
signal, the de-assertion of MII_RXDV constitutes an end-of-frame delimiter.
11.4.1.7 Interframe
The interframe period provides an observation window for a specified amount of time during which no
data activity occurs on the MII. The de-assertion of MII_RXDV on the receive path and the de-assertion
of MII_TXEN in the transmit path indicate the absence of data activity.
11.4.2
The EMAC receiver is designed to work with very little intervention from the CPU.
When the EMAC is enabled, it immediately starts processing receive frames as long as one of the receive
buffer complete interrupt flags is clear. If both RXACIF and RXBCIF are clear, receive buffer A is used
first. If one flag is set, reception occurs on the buffer with the cleared flag. If both flags are set, no data is
stored to the received buffers.
When MII_RXDV asserts, the receiver first checks for a valid PA/SFD sequence. If the PA/SFD is valid,
it is stripped and the frame is processed by the receiver. If a valid PA/SFD is not found, the frame is
ignored.
The receiver checks for at least one byte matching the SFD (10101011). Zero or more PA bytes sent before
the SFD byte are acceptable, but if an invalid PA is detected prior to the SFD byte, the frame is ignored.
Following the SFD, the EMAC converts the nibble stream to a byte data stream. See
After the first six bytes of the frame have been received, the EMAC performs address recognition on the
frame. See
goes idle, the receive buffer stops receiving data, and the receive end-of-frame pointer is invalid. If address
recognition accepts the frame, the receive buffer continues to receive data.
After the first 14 bytes of the frame have been received, the EMAC performs type/length recognition on
the frame. See
the receiver goes idle, the receive buffer stops receiving data, and the receive end-of-frame pointer is
invalid. If type/length recognition accepts the frame, the receive buffer continues to receive data.
Freescale Semiconductor
Receiver
Section 11.4.2.1, “Address
Section 11.4.2.2, “Type/Length
MC9S12NE64 Data Sheet, Rev. 1.1
Recognition.” If address recognition rejects the frame, the receiver
Recognition.”
If type/length recognition rejects the frame,
0
coefficient as the last bit.
Figure
Functional Description
11-23.
333
31
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