MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 96
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 2 64 Kbyte Flash Module (S12FTS64KV3)
2.4.1.3.5
The mass erase command is used to erase a Flash memory block using an embedded algorithm. If the Flash
block to be erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass
erase command will not launch. After the mass erase command has successfully launched, the CCIF flag
in the FSTAT register will set after the mass erase operation has completed unless a second command has
been buffered.
96
Clock Register
Loaded
Check
Mass Erase Command
Protection
Violation Check
Access
Error Check
Address, Data,
Command
Buffer Empty Check
Bit Polling for
Command
Completion Check
Read: Register FCLKDIV
1.
2.
3.
Bit FDIVLD set?
Figure 2-26. Example Mass Erase Command Flow
yes
Write: Flash Block Address
and Dummy Data
Write: Register FCMD
Mass Erase Command 0x41
Write: Register FSTAT
Clear bit CBEIF 0x80
Read: Register FSTAT
no
no
no
ACCERR
yes
MC9S12NE64 Data Sheet, Rev. 1.1
PVIOL
CBEIF
Set?
Set?
Set?
EXIT
Write: Register FCLKDIV
CCIF
Bit
Set?
Bit
Bit
Bit
no
yes
yes
yes
no
Write: Register FSTAT
Clear bit PVIOL 0x20
Clear bit ACCERR 0x10
Write: Register FSTAT
NOTE: command write sequence
aborted by writing 0x00 to
FSTAT register.
NOTE: command write sequence
aborted by writing 0x00 to
FSTAT register.
Read: Register FSTAT
Next Write?
yes
no
Freescale Semiconductor
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