MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 143

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

4.2
This section lists and describes the signals that connect off chip.
4.2.1
These pins provides operating voltage (V
the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required V
and V
4.2.2
A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter
to eliminate the VCO input ripple. The value of the external filter network and the reference frequency
determines the speed of the corrections and the stability of the PLL. Refer to the device overview chapter
for calculation of PLL loop filter (XFC) components. If PLL usage is not required the XFC pin must be
tied to V
Freescale Semiconductor
1
Refer to the device overview section for availability of the low-voltage reset feature.
SSPLL
XCLKS
EXTAL
XTAL
DDPLL
External Signal Description
RESET
V
V
V
XFC — PLL Loop Filter Pin
must be connected properly.
XFC
DDPLL
SSPLL
DDPLL
Regulator
Monitor
Oscil-
.
Voltage
Clock
lator
, V
SSPLL
OSCCLK
PLL
CRG
Power-on Reset
Low Voltage Reset
— PLL Operating Voltage, PLL Ground
PLLCLK
Figure 4-1. CRG Block Diagram
CM fail
MC9S12NE64 Data Sheet, Rev. 1.1
DDPLL
) and ground (V
Clock and Reset
1
Clock Quality
COP
Registers
Control
Checker
Generator
Reset
SSPLL
RTI
) for the PLL circuitry. This allows
Real-Time Interrupt
PLL Lock Interrupt
Self-Clock Mode
Oscillator Clock
System Reset
External Signal Description
Core Clock
Bus Clock
Interrupt
DDPLL
143