MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 377
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Functional Description
12.4.5.2 Wait Mode
If the MCU executes a WAIT instruction with the EPHYWAI bit set, the EPHY will be powered down and
all internal MII registers reset to their default state. Upon exiting STOP mode the EPHY will exit the
power-down state and latch the values previously written to the EPHYCTL0 and EPHYCTL1 registers.
The MII registers must be re-initialized after the start-up delay (t
) has expired.
Start-up
12.4.5.3 MII Power Down
This mode disconnects the PHY from the network interface (three-state receiver and driver pins).
Setting bit 0.11 of the port enters this mode. In this mode, the management interface is accessible but all
internal chip functions are in a zero power state.
In this mode all analog blocks except the PLL clock generator and band gap reference are in low power
mode. All digital blocks except the MDIO interface and management registers are inactive.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
377
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