MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 209
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Note: The read portion of the left justified result data registers has been divided to show the bit position when reading 10-bit
Unimplemente
Unimplemente
Unimplemente
ATDSTAT1
ATDDR0H
ATDDR1H
ATDDR2H
ATDDR3H
ATDDR0L
ATDDR1L
ATDDR2L
ATDDIEN
Register
PORTAD
Name
and 8-bit conversion data. For more detailed information refer to
(ATDDRx)”.
d
d
d
10-BIT BIT 9 MSB
10-BIT
10-BIT BIT 9 MSB
10-BIT
10-BIT BIT 9 MSB
10-BIT
10-BIT BIT 9 MSB
8-BIT
8-BIT
8-BIT
8-BIT
8-BIT
8-BIT
8-BIT
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
BIT 7 MSB
BIT 7 MSB
BIT 7 MSB
BIT 7 MSB
PTAD7
CCF7
BIT 1
BIT 1
BIT 1
Bit 7
IEN7
U
U
U
Figure 7-2. ATD Register Summary (Sheet 2 of 5)
= Unimplemented or Reserved
PTAD6
CCF6
BIT 8
BIT 6
BIT 0
BIT 8
BIT 6
BIT 0
BIT 8
BIT 6
BIT 0
BIT 8
BIT 6
IEN6
U
U
U
6
MC9S12NE64 Data Sheet, Rev. 1.1
Left Justified Result Data
PTAD5
CCF5
BIT 7
BIT 5
BIT 7
BIT 5
BIT 7
BIT 5
BIT 7
BIT 5
IEN5
5
0
0
0
0
0
0
PTAD4
CCF4
BIT 6
BIT 4
BIT 6
BIT 4
BIT 6
BIT 4
BIT 6
BIT 4
IEN4
4
0
0
0
0
0
0
Section 7.3.2.13, “ATD Conversion Result Registers
PTAD3
CCF3
BIT 5
BIT 3
BIT 5
BIT 3
BIT 5
BIT 3
BIT 5
BIT 3
IEN3
3
0
0
0
0
0
0
Memory Map and Register Definition
PTAD2
CCF2
BIT 4
BIT 2
BIT 4
BIT 2
BIT 4
BIT 2
BIT 4
BIT 2
IEN2
2
0
0
0
0
0
0
PTAD1
CCF1
BIT 3
BIT 1
BIT 3
BIT 1
BIT 3
BIT 1
BIT 3
BIT 1
IEN1
1
0
0
0
0
0
0
PTAD0
CCF0
BIT 2
BIT 0
BIT 2
BIT 0
BIT 2
BIT 0
BIT 2
BIT 0
IEN0
Bit 0
0
0
0
0
0
0
209
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