MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 474
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MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 18 Debug Module (DBGV1)
18.3
A summary of the registers associated with the DBG sub-block is shown in
descriptions of the registers and bits are given in the subsections that follow.
18.3.1
18.3.2
This section consists of the DBG register descriptions in address order. Most of the register bits can be
written to in either BKP or DBG mode, although they may not have any effect in one of the modes.
However, the only bits in the DBG module that can be written while the debugger is armed (ARM = 1) are
DBGEN and ARM
474
DBGSC
DBGC1
Name
Memory Map and Register Definition
Address
1
Offset
Module Memory Map
Register Descriptions
A
B
E
F
4
5
6
8
9
W
W
R
R
Debug Control Register (DBGC1)
Debug Status and Control Register (DBGSC)
Debug Trace Buffer Register High (DBGTBH)
Debug Trace Buffer Register Low (DBGTBL)
Debug Control Register 2 (DBGC2) / (BKPCT0)
Debug Control Register 3 (DBGC3) / (BKPCT1)
Debug Comparator A Extended Register (DBGCAX) / (/BKP0X)
Debug Comparator A Register High (DBGCAH) / (BKP0H)
Debug Comparator A Register Low (DBGCAL) / (BKP0L)
Debug Comparator B Extended Register (DBGCBX) / (BKP1X)
Debug Comparator B Register High (DBGCBH) / (BKP1H)
Debug Comparator B Register Low (DBGCBL) / (BKP1L)
Debug Count Register (DBGCNT)
Debug Comparator C Extended Register (DBGCCX)
Debug Comparator C Register High (DBGCCH)
Debug Comparator C Register Low (DBGCCL)
DBGEN
Bit 7
AF
= Unimplemented or Reserved
Figure 18-3. DBG Register Summary
ARM
BF
Table 18-2. DBGV1 Memory Map
6
MC9S12NE64 Data Sheet, Rev. 1.1
TRGSEL
CF
5
Use
BEGIN
4
0
DBGBRK
3
Figure
2
0
TRG
18-3. Detailed
Freescale Semiconductor
Access
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAPMOD
R
R
R
Bit 0
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