MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 356
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 12 Ethernet Physical Transceiver (EPHYV2)
RAN — Restart Auto-Negotiation
DPLX — Duplex Mode
COLTEST — Collision Test
12.3.3.2 Status Register
This register advertises the capabilities of the port to the MII.
Read: Anytime
Write: Writes have no effect
100T4 —100BASE-T4
100XFD —100BASE-TX Full-Duplex
356
MII Register Address 1 (%00001)
RESET:
The RAN bit determines when the A/N process can start processing.
This mode can be selected by either the auto-negotiation process or manual duplex selection. Manual
duplex selection is allowed only while the auto-negotiation process is disabled (ANE=0). While the
auto-negotiation process is enabled (ANE = 1), the state of DPLX has no effect on the link
configuration. While loopback mode is asserted (LOOPBACK =1), the value of DPLX will have no
effect on the PHY.
The collision test function will be enabled only if the loopback mode of operation is also selected
(LOOPBACK = 1).
W
This function is not implemented in the EPHY module.
R
1 = When auto-negotiation is enabled (ANE=1), the auto-negotiation process will be restarted.
0 = Normal operation.
1 = Indicates full-duplex mode
0 = Indicates half-duplex mode
1 = Forces the PHY to assert the MII_COL signal within 512 bit times from the assertion of
0 = Normal operation
1 = Indicates PHY supports 100BASE-T4 transmission
0 = Indicates the PHY does not support 100BASE-T4 transmission
1 = Indicates PHY supports 100BASE-TX full-duplex mode
0 = Indicates PHY does not support 100BASE-TX full-duplex mode
100
15
T4
0
After auto-negotiation indicates that it has been initialized, this bit is cleared. When bit ANE
is cleared to indicate auto-negotiation is disabled, RAN must also be 0.
MII_TXEN and de-assert MII_COL within 4 bit times of MII_TXEN being de-asserted.
= Unimplemented or Reserved
100X
14
FD
1
100X
13
HD
1
10T
12
FD
1
10T
11
HD
1
MC9S12NE64 Data Sheet, Rev. 1.1
Figure 12-7. Status Register
10
0
0
9
0
0
8
0
0
7
0
0
SUP
PRE
6
1
COMP
AN
5
0
REM
FLT
4
0
ABL
AN
Freescale Semiconductor
3
1
STST
LNK
2
0
JAB
DT
1
0
CAP
EX
0
1
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