MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 406
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MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 15 Multiplexed External Bus Interface (MEBIV3)
15.3.2.7
Read: Anytime when register is in the map
Write: Anytime when register is in the map
Data direction register E is associated with port E. For bits in port E that are configured as general-purpose
I/O lines, DDRE determines the primary direction of each of these pins. A 1 causes the associated bit to
be an output and a 0 causes the associated bit to be an input. Port E bit 1 (associated with IRQ) and bit 0
(associated with XIRQ) cannot be configured as outputs. Port E, bits 1 and 0, can be read regardless of
whether the alternate interrupt function is enabled. The value in a DDR bit also affects the source of data
for reads of the corresponding PORTE register. If the DDR bit is 0 (input) the buffered pin input state is
read. If the DDR bit is 1 (output) the associated port data register bit state is read.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally. Also, it is not in the map in expanded modes while the EME control bit
is set.
406
Reset
DDRE
Field
7:2
W
R
Bit 7
Data Direction Port E
0 Configure the corresponding I/O pin as an input
1 Configure the corresponding I/O pin as an output
Note: It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from inputs to
Data Direction Register E (DDRE)
0
7
outputs, the data may have extra transitions during the write. It is best to initialize PORTE before enabling
as outputs.
= Unimplemented or Reserved
6
0
6
Figure 15-11. Data Direction Register E (DDRE)
Table 15-5. DDRE Field Descriptions
MC9S12NE64 Data Sheet, Rev. 1.1
5
0
5
4
0
4
Description
3
0
3
Bit 2
0
2
Freescale Semiconductor
0
0
1
0
0
0
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