MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 287
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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10.3.2.2
Read and write anytime
Freescale Semiconductor
IBC[7:0]
Reset
Field
7:0
W
R
IBC7
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in
IIC Frequency Divider Register (IBFD)
0
7
Table
10-3.
IBC5-3
(bin)
000
001
010
011
100
101
110
111
IBC6
Figure 10-4. IIC Bus Frequency Divider Register (IBFD)
= Unimplemented or Reserved
0
6
Table 10-3. I-Bus Tap and Prescale Values
scl2start
(clocks)
IBC2-0
Table 10-2. IBFD Field Descriptions
(bin)
000
001
010
011
100
101
110
111
126
14
30
62
IBC5
2
2
2
6
MC9S12NE64 Data Sheet, Rev. 1.1
0
5
IBC4
scl2stop
SCL Tap
(clocks)
(clocks)
0
4
129
10
12
15
17
33
65
5
6
7
8
9
7
7
9
9
Description
IBC3
0
3
SDA Tap
(clocks)
(clocks)
scl2tap
126
14
30
62
1
1
2
2
3
3
4
4
4
4
6
6
IBC2
0
2
Memory Map and Register Definition
(clocks)
tap2tap
128
16
32
64
1
2
4
8
IBC1
0
1
IBC0
0
0
287
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