MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 357
![IC MCU 25MHZ ETHERNT/PHY 112LQFP](/photos/12/20/122046/mc9s12ne64cpv_sml.jpg)
MC9S12NE64CPV
Manufacturer Part Number
MC9S12NE64CPV
Description
IC MCU 25MHZ ETHERNT/PHY 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64CPV
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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100XHD —100BASE-TX Half-Duplex
10TFD —10BASE-T Full-Duplex
10THD —10BASE-T Half-Duplex
SUPPRE —MF Preamble Suppression
ANCOMP —Auto-Negotiation Complete
REMFLT — Remote Fault
ANABL — Auto-Negotiation Ability
LNKSTST — Link Status
Freescale Semiconductor
To inform the management interface (MI) that it has completed processing, ANCOMP is set by the
A/N process. After it has been started, the auto-negotiation process uses link code words to exchange
capability information and establish the highest common denominator (HCD) for link transactions.
Possible remote faults (RF)
After it is set, REMFLT is cleared each time register 1 is read via the management interface. REMFLT
is also cleared by a PHY reset.
The PHY sets this bit when it determines that a valid link has been established. The occurrence of a
link failure will cause LNKSTST to be cleared. After it has been cleared, it remains cleared until it is
read via the management interface.
1 = Indicates the PHY supports 100BASE-TX half-duplex mode
0 = Indicates the PHY does not support 100BASE-TX half-duplex mode
1 = Indicates the PHY supports 10BASE-T full-duplex mode
0 = Indicates the PHY does not support 10BASE-T full-duplex mode
1 = Indicates the PHY supports 10BASE-T half-duplex mode
0 = Indicates the PHY does not support 10BASE-T half-duplex mode
1 = Indicates that management frames are not required to contain the preamble stream
0 = Indicates that management frames are required to contain the preamble stream
1 = Indicates that the auto-negotiation process has completed and that the contents of registers 4
0 = Indicates that the auto-negotiation process has not completed and that the contents of registers
1 = Indicates that a remote fault condition has been detected.
0 = No fault detected
1 = Indicates that PHY has auto-negotiation ability
0 = Indicates that PHY does not have auto-negotiation ability
1 = Indicates a valid link has been established
0 = Indicates a valid link has NOT been established
a) The link partner transmits the RF bit (5.13=1)
b) Link partner protocol is not 00001 (5.4:0)
c) Link partner advertises only T4 capability (5.9:5)
d) No common operation mode found between PHY and the link partner.
through 7 are valid.
4 through 7 are not valid
MC9S12NE64 Data Sheet, Rev. 1.1
Memory Map and Register Descriptions
357
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