DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1603

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Item
7.4.6 PC Trace
7.5 Usage Notes
Figure 8.15 Example of DTC
Operation Timing:
Normal or Repeat Transfer
(Activated by IRQ; Iφ: Bφ: Pφ =1:
1/2: 1/2; Data Transferred from
On-Chip Peripheral Module to On-
Chip RAM; Transfer Information is
Written in 3 Cycles)
8.5.9 DTC Bus Release Timing
Page Revision (See Manual for Details)
162
169
203
206
Amended
3. BRSR and BRDR have four pairs of queue
4. Since four pairs (eight pairs for the F-ZTAT version
Added
9. When the DTC or DMAC is in operation, the UBC
Added
Amended
The DTC requests the bus mastership to the bus arbiter
when an activation request occurs. The DTC releases
the bus after a vector read, NOP cycle generation after
a vector read, transfer information read, a single data
transfer, or transfer information writeback. The DTC
does not release the bus mastership during transfer
information read, single data transfer, or transfer
information writeback.
cannot correctly determine access to the external
space by the CPU via the I bus. To determine access
to the external space via the I bus in the above
situation, select all bus masters. This makes it
impossible to determine conditions of access with
specified bus masters. However, when a bus master
can be inferred from data values, the relevant data
values can be included as a condition that indicates a
particular bus master.
structures (eight pairs for the F-ZTAT version
supporting full functions of E10A). The top of queues
is read first when the address stored in the PC trace
register is read. ….
supporting full functions of E10A) of queue are
shared with the AUD, set the PCTE bit in BRCR to 1
after setting the MSTP25 bit in STBCR5 to 0 and the
AUDSRST bit in STBCR6 to 1. ….
Rev. 3.00 May 17, 2007 Page 1545 of 1582
REJ09B0181-0300